The push for decreased die sizes and higher performance devices steadily lowers target minimum feature sizes and dictates steadily decreasing error tolerances. Accordingly, critical dimension and overlay error control limits in lithography will continue to decrease, presenting a challenging obstacle for semiconductor manufacturing.
Critical dimension error specifications and overlay error specifications are established for a technology based upon layout design rules, device performance and reliability requirements. Line edge placement specifications, which include both critical dimension error and overlay error, are also established based upon layout design rules, device performance and reliability requirements.
In the fabrication processes critical dimension error and overlay error are considered independently. More particularly, any lot of semiconductor wafers that does not meet the critical dimension specification is reworked (regardless of the overlay error in that lot). Similarly, any lot of semiconductor wafers that does not meet the overlay specification is reworked (regardless of the critical dimension error in that lot).
In conventional methodologies the overlay specification is determined using a worst-case critical dimension error. However, by allowing for worst-case critical dimension error an overly restrictive overlay specification is obtained. This can result in lots of semiconductor wafers being reworked when the semiconductor wafers in the lot do not exceed the allowable line edge placement specification for the lot. This increases rework rates, expends unnecessary manufacturing resources, extends fabrication time and results in increased manufacturing costs.
Accordingly, there is a need for methods that allow for accurately determining critical dimension specifications and overlay specifications based on the line edge placement specifications established for the manufacturing process. Moreover, there is a need for methods that allow for accurately determining whether or not a particular lot of semiconductor wafers needs to be reworked. The present invention meets the above needs.